ASCII in. Morse out. One clock domain.

Problem

Encode human-readable input as timed hardware behavior.

The system must accept a standard ASCII character, look up its Morse representation and length, and emit a correctly timed dot/dash sequence while keeping the board interface stable and observable.

RTL architecture

Small modules with explicit timing responsibilities.

Modules

Decode, display, condition, and sequence.

• ASCII lookup/decoder: maps each supported input to Morse symbols and a valid sequence length.
• ASCII-to-seven-segment decoder: makes the selected character visible on the board.
• Display multiplexer: refreshes multi-digit seven-segment output.
• Button path: synchronizes the asynchronous input, debounces it, and produces a clean edge event.
• Clock/tick enable generator: produces timing events without creating a second logic clock.
• Morse finite-state machine: sequences dots, dashes, and gaps from lookup output.

Important decision

Use clock enables instead of a generated clock.

The entire design remains in the board’s 100 MHz clock domain. Slower behavior is driven by tick/clock-enable pulses. That avoids introducing a second clock network through ordinary fabric, simplifies timing analysis, and keeps crossings out of the core control path.

Verification

Check logic before trusting the board.

The testbench exercises supported inputs and observes the FSM sequence, output timing, and termination behavior. Physical testing then checks the integrated path from board controls through seven-segment feedback and Morse output.

Vivado flow

From behavioral model to physical device.

Results

Modular RTL with physical validation.

Limitations + next steps

Publish the final artifact, not an approximate one.

The case study intentionally withholds a repository link until the public repository is confirmed against the final design. Next steps include a verified code release, annotated waveform, board demo, timing summary, and a concise explanation of edge cases.